min

help

Click on a value or block to toggle highlighting of that value/block and its uses. (Values and blocks are highlighted by ID, and IDs of dead items may be reused, so not all highlights necessarily correspond to the clicked item.)

Faded out values and blocks are dead code that has not been eliminated.

Values printed in italics have a dependency cycle.

CFG: Dashed edge is for unlikely branches. Blue color is for backward edges. Edge with a dot means that this edge follows the order in which blocks were laidout.

sources

 
 
22
23
24
25
26
27
 
/root/main.go
func min(x, y int) int {
	if x < y {
		return x
	}
	return y
}

AST

buildssa-enter
. AS l(22)
. . NAME-main.~r2 a(true) g(1) l(22) x(16) class(PPARAMOUT) esc(no) int
buildssa-body
. IF l(23) tc(1)
. . LT l(23) tc(1) bool
. . . NAME-main.x a(true) g(2) l(22) x(0) class(PPARAM) esc(no) tc(1) used int
. . . NAME-main.y a(true) g(3) l(22) x(8) class(PPARAM) esc(no) tc(1) used int
. IF-body
. . RETURN l(24) tc(1)
. . RETURN-list
. . . AS l(24) tc(1)
. . . . NAME-main.~r2 a(true) g(1) l(22) x(16) class(PPARAMOUT) esc(no) int
. . . . NAME-main.x a(true) g(2) l(22) x(0) class(PPARAM) esc(no) tc(1) used int
 
. RETURN l(26) tc(1)
. RETURN-list
. . AS l(26) tc(1)
. . . NAME-main.~r2 a(true) g(1) l(22) x(16) class(PPARAMOUT) esc(no) int
. . . NAME-main.y a(true) g(3) l(22) x(8) class(PPARAM) esc(no) tc(1) used int
buildssa-exit
 

start

  • b1:
    • v1 (?) = InitMem <mem>
    • v2 (?) = SP <uintptr>
    • v3 (?) = SB <uintptr>
    • v4 (?) = LocalAddr <*int> {x} v2 v1
    • v5 (?) = LocalAddr <*int> {y} v2 v1
    • v6 (?) = LocalAddr <*int> {~r2} v2 v1
    • v7 (22) = Arg <int> {x} (x[int])
    • v8 (22) = Arg <int> {y} (y[int])
    • v9 (?) = Const64 <int> [0]
    • v10 (23) = Less64 <bool> v7 v8
  • If v10 → b3 b2 (23)
  • b2: ← b1
    • v15 (26) = Copy <int> v8 (y[int])
    • v16 (26) = Copy <mem> v1
    • v17 (26) = VarDef <mem> {~r2} v16
    • v18 (26) = Store <mem> {int} v6 v15 v17
  • Ret v18 (+26)
  • b3: ← b1
    • v11 (24) = Copy <int> v7 (x[int])
    • v12 (24) = Copy <mem> v1
    • v13 (24) = VarDef <mem> {~r2} v12
    • v14 (24) = Store <mem> {int} v6 v11 v13
  • Ret v14 (+24)
  • name x[int]: v7 v11
  • name y[int]: v8 v15

    • number lines [28800 ns]

    b1 b1 If b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v3 (?) = SB <uintptr>
      • v4 (?) = LocalAddr <*int> {x} v2 v1
      • v5 (?) = LocalAddr <*int> {y} v2 v1
      • v6 (?) = LocalAddr <*int> {~r2} v2 v1
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v9 (?) = Const64 <int> [0]
      • v10 (+23) = Less64 <bool> v7 v8
    • If v10 → b3 b2 (23)
    • b2: ← b1
      • v15 (26) = Copy <int> v8 (y[int])
      • v16 (26) = Copy <mem> v1
      • v17 (26) = VarDef <mem> {~r2} v16
      • v18 (+26) = Store <mem> {int} v6 v15 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v11 (24) = Copy <int> v7 (x[int])
      • v12 (24) = Copy <mem> v1
      • v13 (24) = VarDef <mem> {~r2} v12
      • v14 (+24) = Store <mem> {int} v6 v11 v13
    • Ret v14 (+24)
  • name x[int]: v7 v11
  • name y[int]: v8 v15

    • early phielim [23900 ns]

    b1 b1 If b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v3 (?) = SB <uintptr>
      • v4 (?) = LocalAddr <*int> {x} v2 v1
      • v5 (?) = LocalAddr <*int> {y} v2 v1
      • v6 (?) = LocalAddr <*int> {~r2} v2 v1
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v9 (?) = Const64 <int> [0]
      • v10 (+23) = Less64 <bool> v7 v8
    • If v10 → b3 b2 (23)
    • b2: ← b1
      • v15 (26) = Copy <int> v8 (y[int])
      • v16 (26) = Copy <mem> v1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = Store <mem> {int} v6 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v11 (24) = Copy <int> v7 (x[int])
      • v12 (24) = Copy <mem> v1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = Store <mem> {int} v6 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7 v11
  • name y[int]: v8 v15

    • early copyelim [23800 ns]

    b1 b1 If b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v3 (?) = SB <uintptr>
      • v4 (?) = LocalAddr <*int> {x} v2 v1
      • v5 (?) = LocalAddr <*int> {y} v2 v1
      • v6 (?) = LocalAddr <*int> {~r2} v2 v1
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v9 (?) = Const64 <int> [0]
      • v10 (+23) = Less64 <bool> v7 v8
    • If v10 → b3 b2 (23)
    • b2: ← b1
      • v15 (26) = Copy <int> v8
      • v16 (26) = Copy <mem> v1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = Store <mem> {int} v6 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v11 (24) = Copy <int> v7
      • v12 (24) = Copy <mem> v1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = Store <mem> {int} v6 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7 v7
  • name y[int]: v8 v8

    • early deadcode [27500 ns]

    b1 b1 If b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v6 (?) = LocalAddr <*int> {~r2} v2 v1
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v10 (+23) = Less64 <bool> v7 v8
    • If v10 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = Store <mem> {int} v6 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = Store <mem> {int} v6 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • short circuit [20800 ns]

    b1 b1 If b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v6 (?) = LocalAddr <*int> {~r2} v2 v1
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v10 (+23) = Less64 <bool> v7 v8
    • If v10 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = Store <mem> {int} v6 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = Store <mem> {int} v6 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • decompose args [25000 ns]

    b1 b1 If b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v6 (?) = LocalAddr <*int> {~r2} v2 v1
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v10 (+23) = Less64 <bool> v7 v8
    • If v10 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = Store <mem> {int} v6 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = Store <mem> {int} v6 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • decompose user [22100 ns]

    b1 b1 If b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v6 (?) = LocalAddr <*int> {~r2} v2 v1
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v10 (+23) = Less64 <bool> v7 v8
    • If v10 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = Store <mem> {int} v6 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = Store <mem> {int} v6 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • opt [33400 ns]

    b1 b1 If b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v6 (?) = LocalAddr <*int> {~r2} v2 v1
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v10 (+23) = Less64 <bool> v7 v8
    • If v10 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = Store <mem> {int} v6 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = Store <mem> {int} v6 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • zero arg cse [32700 ns]

    b1 b1 If b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v6 (?) = LocalAddr <*int> {~r2} v2 v1
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v10 (+23) = Less64 <bool> v7 v8
    • If v10 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = Store <mem> {int} v6 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = Store <mem> {int} v6 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • opt deadcode [39600 ns]

    b1 b1 If b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v6 (?) = LocalAddr <*int> {~r2} v2 v1
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v10 (+23) = Less64 <bool> v7 v8
    • If v10 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = Store <mem> {int} v6 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = Store <mem> {int} v6 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • generic cse [45400 ns]

    b1 b1 If b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v6 (?) = LocalAddr <*int> {~r2} v2 v1
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v10 (+23) = Less64 <bool> v7 v8
    • If v10 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = Store <mem> {int} v6 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = Store <mem> {int} v6 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • phiopt [24900 ns]

    b1 b1 If b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v6 (?) = LocalAddr <*int> {~r2} v2 v1
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v10 (+23) = Less64 <bool> v7 v8
    • If v10 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = Store <mem> {int} v6 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = Store <mem> {int} v6 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • nilcheckelim [28900 ns]

    b1 b1 If b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v6 (?) = LocalAddr <*int> {~r2} v2 v1
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v10 (+23) = Less64 <bool> v7 v8
    • If v10 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = Store <mem> {int} v6 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = Store <mem> {int} v6 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • prove [66400 ns]

    b1 b1 If b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v6 (?) = LocalAddr <*int> {~r2} v2 v1
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v10 (+23) = Less64 <bool> v7 v8
      • v12 (?) = Const64 <int64> [0]
    • If v10 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = Store <mem> {int} v6 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = Store <mem> {int} v6 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • fuse plain [27200 ns]

    b1 b1 If b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v6 (?) = LocalAddr <*int> {~r2} v2 v1
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v10 (+23) = Less64 <bool> v7 v8
      • v12 (?) = Const64 <int64> [0]
    • If v10 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = Store <mem> {int} v6 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = Store <mem> {int} v6 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • decompose builtin [37600 ns]

    b1 b1 If b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v6 (?) = LocalAddr <*int> {~r2} v2 v1
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v10 (+23) = Less64 <bool> v7 v8
      • v12 (?) = Const64 <int64> [0]
    • If v10 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = Store <mem> {int} v6 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = Store <mem> {int} v6 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • softfloat [20800 ns]

    b1 b1 If b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v6 (?) = LocalAddr <*int> {~r2} v2 v1
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v10 (+23) = Less64 <bool> v7 v8
      • v12 (?) = Const64 <int64> [0]
    • If v10 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = Store <mem> {int} v6 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = Store <mem> {int} v6 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • late opt [33500 ns]

    b1 b1 If b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v6 (?) = LocalAddr <*int> {~r2} v2 v1
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v10 (+23) = Less64 <bool> v7 v8
      • v12 (?) = Const64 <int64> [0]
    • If v10 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = Store <mem> {int} v6 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = Store <mem> {int} v6 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • dead auto elim [22700 ns]

    b1 b1 If b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v6 (?) = LocalAddr <*int> {~r2} v2 v1
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v10 (+23) = Less64 <bool> v7 v8
      • v12 (?) = Const64 <int64> [0]
    • If v10 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = Store <mem> {int} v6 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = Store <mem> {int} v6 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • generic deadcode [154800 ns]

    b1 b1 If b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v6 (?) = LocalAddr <*int> {~r2} v2 v1
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v10 (+23) = Less64 <bool> v7 v8
    • If v10 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = Store <mem> {int} v6 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = Store <mem> {int} v6 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • check bce [25100 ns]

    b1 b1 If b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v6 (?) = LocalAddr <*int> {~r2} v2 v1
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v10 (+23) = Less64 <bool> v7 v8
    • If v10 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = Store <mem> {int} v6 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = Store <mem> {int} v6 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • branchelim [21100 ns]

    b1 b1 If b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v6 (?) = LocalAddr <*int> {~r2} v2 v1
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v10 (+23) = Less64 <bool> v7 v8
    • If v10 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = Store <mem> {int} v6 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = Store <mem> {int} v6 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • fuse [24700 ns]

    b1 b1 If b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v6 (?) = LocalAddr <*int> {~r2} v2 v1
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v10 (+23) = Less64 <bool> v7 v8
    • If v10 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = Store <mem> {int} v6 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = Store <mem> {int} v6 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • dse [26000 ns]

    b1 b1 If b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v6 (?) = LocalAddr <*int> {~r2} v2 v1
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v10 (+23) = Less64 <bool> v7 v8
    • If v10 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = Store <mem> {int} v6 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = Store <mem> {int} v6 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • writebarrier [24300 ns]

    b1 b1 If b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v6 (?) = LocalAddr <*int> {~r2} v2 v1
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v10 (+23) = Less64 <bool> v7 v8
    • If v10 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = Store <mem> {int} v6 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = Store <mem> {int} v6 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • lower [47000 ns]

    b1 b1 LT b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v6 (?) = MOVDaddr <*int> {~r2} v2
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v16 (+23) = MOVDconst <uint64> [0]
      • v15 (+23) = MOVDconst <uint64> [1]
      • v9 (+23) = CMP <flags> v7 v8
      • v10 (+23) = MOVDLT <bool> v16 v15 v9
      • v12 (+23) = CMPWconst <flags> [0] v10
    • LT v9 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = MOVDstore <mem> {~r2} v2 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = MOVDstore <mem> {~r2} v2 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • lowered cse [30500 ns]

    b1 b1 LT b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v6 (?) = MOVDaddr <*int> {~r2} v2
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v16 (+23) = MOVDconst <uint64> [0]
      • v15 (+23) = MOVDconst <uint64> [1]
      • v9 (+23) = CMP <flags> v7 v8
      • v10 (+23) = MOVDLT <bool> v16 v15 v9
      • v12 (+23) = CMPWconst <flags> [0] v10
    • LT v9 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = MOVDstore <mem> {~r2} v2 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = MOVDstore <mem> {~r2} v2 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • elim unread autos [30300 ns]

    b1 b1 LT b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v6 (?) = MOVDaddr <*int> {~r2} v2
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v16 (+23) = MOVDconst <uint64> [0]
      • v15 (+23) = MOVDconst <uint64> [1]
      • v9 (+23) = CMP <flags> v7 v8
      • v10 (+23) = MOVDLT <bool> v16 v15 v9
      • v12 (+23) = CMPWconst <flags> [0] v10
    • LT v9 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = MOVDstore <mem> {~r2} v2 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = MOVDstore <mem> {~r2} v2 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • lowered deadcode [43300 ns]

    b1 b1 LT b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v9 (+23) = CMP <flags> v7 v8
    • LT v9 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = MOVDstore <mem> {~r2} v2 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = MOVDstore <mem> {~r2} v2 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • checkLower [21100 ns]

    b1 b1 LT b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v9 (+23) = CMP <flags> v7 v8
    • LT v9 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = MOVDstore <mem> {~r2} v2 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = MOVDstore <mem> {~r2} v2 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • late phielim [25400 ns]

    b1 b1 LT b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v9 (+23) = CMP <flags> v7 v8
    • LT v9 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = MOVDstore <mem> {~r2} v2 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = MOVDstore <mem> {~r2} v2 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • late copyelim [20400 ns]

    b1 b1 LT b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v9 (+23) = CMP <flags> v7 v8
    • LT v9 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = MOVDstore <mem> {~r2} v2 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = MOVDstore <mem> {~r2} v2 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • tighten [39400 ns]

    b1 b1 LT b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v9 (+23) = CMP <flags> v7 v8
    • LT v9 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = MOVDstore <mem> {~r2} v2 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = MOVDstore <mem> {~r2} v2 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • late deadcode [47500 ns]

    b1 b1 LT b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v9 (+23) = CMP <flags> v7 v8
    • LT v9 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = MOVDstore <mem> {~r2} v2 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = MOVDstore <mem> {~r2} v2 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • critical [21700 ns]

    b1 b1 LT b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v9 (+23) = CMP <flags> v7 v8
    • LT v9 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = MOVDstore <mem> {~r2} v2 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = MOVDstore <mem> {~r2} v2 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • phi tighten [20700 ns]

    b1 b1 LT b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v9 (+23) = CMP <flags> v7 v8
    • LT v9 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = MOVDstore <mem> {~r2} v2 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = MOVDstore <mem> {~r2} v2 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • likelyadjust [21900 ns]

    b1 b1 LT b2 b2 Ret b1->b2 1 b3 b3 Ret b1->b3 0
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v9 (+23) = CMP <flags> v7 v8
    • LT v9 → b3 b2 (23)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = MOVDstore <mem> {~r2} v2 v8 v17
    • Ret v18 (+26)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = MOVDstore <mem> {~r2} v2 v7 v13
    • Ret v14 (+24)
  • name x[int]: v7
  • name y[int]: v8

    • layout [24400 ns]

    b1 b1 #0 LT b3 b3 #1 Ret b1->b3 0 b2 b2 #2 Ret b1->b2 1 b3->b2
    • b1:
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v9 (+23) = CMP <flags> v7 v8
    • LT v9 → b3 b2 (23)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = MOVDstore <mem> {~r2} v2 v7 v13
    • Ret v14 (+24)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = MOVDstore <mem> {~r2} v2 v8 v17
    • Ret v18 (+26)
  • name x[int]: v7
  • name y[int]: v8

    • schedule [40600 ns]

    b1 b1 #0 LT b3 b3 #1 Ret b1->b3 0 b2 b2 #2 Ret b1->b2 1 b3->b2
    • b1:
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v9 (+23) = CMP <flags> v7 v8
    • LT v9 → b3 b2 (23)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = MOVDstore <mem> {~r2} v2 v7 v13
    • Ret v14 (+24)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = MOVDstore <mem> {~r2} v2 v8 v17
    • Ret v18 (+26)
  • name x[int]: v7
  • name y[int]: v8

    • late nilcheck [21200 ns]

    b1 b1 #0 LT b3 b3 #1 Ret b1->b3 0 b2 b2 #2 Ret b1->b2 1 b3->b2
    • b1:
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v9 (+23) = CMP <flags> v7 v8
    • LT v9 → b3 b2 (23)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = MOVDstore <mem> {~r2} v2 v7 v13
    • Ret v14 (+24)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = MOVDstore <mem> {~r2} v2 v8 v17
    • Ret v18 (+26)
  • name x[int]: v7
  • name y[int]: v8

    • flagalloc [28800 ns]

    b1 b1 #0 LT b3 b3 #1 Ret b1->b3 0 b2 b2 #2 Ret b1->b2 1 b3->b2
    • b1:
      • v7 (22) = Arg <int> {x} (x[int])
      • v8 (22) = Arg <int> {y} (y[int])
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr>
      • v9 (+23) = CMP <flags> v7 v8
    • LT v9 → b3 b2 (23)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = MOVDstore <mem> {~r2} v2 v7 v13
    • Ret v14 (+24)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = MOVDstore <mem> {~r2} v2 v8 v17
    • Ret v18 (+26)
  • name x[int]: v7
  • name y[int]: v8

    • regalloc [71500 ns]

    b1 b1 #0 LT b3 b3 #1 Ret b1->b3 0 b2 b2 #2 Ret b1->b2 1 b3->b2
    • b1:
      • v7 (22) = Arg <int> {x} : x[int] (x[int])
      • v8 (22) = Arg <int> {y} : y[int] (y[int])
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr> : SP
      • v15 (23) = LoadReg <int> v7 : R0
      • v16 (23) = LoadReg <int> v8 : R1
      • v9 (+23) = CMP <flags> v15 v16
    • LT v9 → b3 b2 (23)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = MOVDstore <mem> {~r2} v2 v15 v13
    • Ret v14 (+24)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = MOVDstore <mem> {~r2} v2 v16 v17
    • Ret v18 (+26)
  • name x[int]: v7
  • name y[int]: v8

    • loop rotate [25200 ns]

    b1 b1 #0 LT b3 b3 #1 Ret b1->b3 0 b2 b2 #2 Ret b1->b2 1 b3->b2
    • b1:
      • v7 (22) = Arg <int> {x} : x[int] (x[int])
      • v8 (22) = Arg <int> {y} : y[int] (y[int])
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr> : SP
      • v15 (23) = LoadReg <int> v7 : R0
      • v16 (23) = LoadReg <int> v8 : R1
      • v9 (+23) = CMP <flags> v15 v16
    • LT v9 → b3 b2 (23)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = MOVDstore <mem> {~r2} v2 v15 v13
    • Ret v14 (+24)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = MOVDstore <mem> {~r2} v2 v16 v17
    • Ret v18 (+26)
  • name x[int]: v7
  • name y[int]: v8

    • stackframe [29600 ns]

    b1 b1 #0 LT b3 b3 #1 Ret b1->b3 0 b2 b2 #2 Ret b1->b2 1 b3->b2
    • b1:
      • v7 (22) = Arg <int> {x} : x[int] (x[int])
      • v8 (22) = Arg <int> {y} : y[int] (y[int])
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr> : SP
      • v15 (23) = LoadReg <int> v7 : R0
      • v16 (23) = LoadReg <int> v8 : R1
      • v9 (+23) = CMP <flags> v15 v16
    • LT v9 → b3 b2 (23)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = MOVDstore <mem> {~r2} v2 v15 v13
    • Ret v14 (+24)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = MOVDstore <mem> {~r2} v2 v16 v17
    • Ret v18 (+26)
  • name x[int]: v7
  • name y[int]: v8

    • trim [24700 ns]

    b1 b1 #0 LT b3 b3 #1 Ret b1->b3 0 b2 b2 #2 Ret b1->b2 1 b3->b2
    • b1:
      • v7 (22) = Arg <int> {x} : x[int] (x[int])
      • v8 (22) = Arg <int> {y} : y[int] (y[int])
      • v1 (?) = InitMem <mem>
      • v2 (?) = SP <uintptr> : SP
      • v15 (23) = LoadReg <int> v7 : R0
      • v16 (23) = LoadReg <int> v8 : R1
      • v9 (+23) = CMP <flags> v15 v16
    • LT v9 → b3 b2 (23)
    • b3: ← b1
      • v13 (24) = VarDef <mem> {~r2} v1
      • v14 (+24) = MOVDstore <mem> {~r2} v2 v15 v13
    • Ret v14 (+24)
    • b2: ← b1
      • v17 (26) = VarDef <mem> {~r2} v1
      • v18 (+26) = MOVDstore <mem> {~r2} v2 v16 v17
    • Ret v18 (+26)
  • name x[int]: v7
  • name y[int]: v8

    • genssa

    # /root/main.go
    00000 (22) TEXT "".min(SB), ABIInternal
    00001 (22) FUNCDATA $0, gclocals·2002e13acf59079a1a5782c918894579(SB)
    00002 (22) FUNCDATA $1, gclocals·2002e13acf59079a1a5782c918894579(SB)
    00003 (22) FUNCDATA $2, gclocals·2002e13acf59079a1a5782c918894579(SB)
    v15
    00004 (+23) PCDATA $0, $0
    v15
    00005 (+23) PCDATA $1, $0
    v15
    00006 (+23) MOVD "".x(R15), R0
    v16
    00007 (23) MOVD "".y+8(R15), R1
    v9
    00008 (23) CMP R0, R1
    b1
    00009 (23) BGE 12
    v14
    00010 (+24) MOVD R0, "".~r2+16(R15)
    b3
    00011 (24) RET
    v18
    00012 (+26) MOVD R1, "".~r2+16(R15)
    b2
    00013 (26) RET
    00014 (?) END